Program concluded · Ran for 12 weeks from 12 August 2024
IEEE CAS Bangalore Chapter · Student Internship Program
Student InternshipProgram 2.0
Exposure to the concepts applied in industry and research.
A mentor-mentee program with the IEEE Bangalore Section · Online, with an in-person final presentation
Starts12 Aug 2024
Duration12 weeks
Team4 members
Open toBachelor’s students
About the program
What is SIP 2.0?
The second edition of the IEEE CAS Bangalore Chapter’s Student Internship Program gave students exposure to the concepts applied in industry and research.
It is a mentor-mentee program: each team is guided personally by experts from industry and academia across Karnataka, working through a project in one of seven themes.
7
Internship themes
19
Mentors
12
Weeks
4
Members per team
Internship domains
Seven themes
01FPGA RTL Design
02Digital Schematics
03VLSI Design
04Formal Verification
05Analog and RF Design
06Embedded and IoT
07AI and ML
Mentors
Guided by industry and academia
Mentors from semiconductor companies and institutions across Karnataka.
Mentor
Institution
Domain
Dr. Sarfraz Hussain
REVA University
Analog and RF Design
Surinder Sood
Arm
Formal Verification
Dr. Shashidhara H R
The National Institute of Engineering
FPGA / RTL Design
Dr. Joseph Anthony Prathap
Presidency University, Bengaluru
FPGA / RTL Design
Rajanikanth
Intel
FPGA / RTL Design
Dr. Javed G S
Intel
Analog and RF Design
Dr. Hemamalini
Vemana Institute of Technology
Embedded and IoT
Dr. Sundari Tribhuvanam
Atria Institute of Technology
DSP, Image Processing, AI & ML
Danish Shaikh
Western Digital
Analog and RF Design
Manoj Dusanapudi
IBM
Architecture, micro-architecture, post-silicon validation, functional verification
Dr. Leena Chandrashekar
RNSIT
AI and ML
Aloke Kumar Das
Lab and Lectures Semiconductor
VLSI Design
Dr. Shailendra Kumar Mishra
REVA University
AI and ML
Hariprasad Bhat
Lekha Wireless Solutions
FPGA / RTL Design
Girish A. Subbarao
SemiconAdept Consulting
Embedded systems, VLSI, digital electronics
Gunjan Mandal
Intel Technology
Analog and RF Design
Sandeep
STMicroelectronics
AI and ML
Mahesh Penugonda
STMicroelectronics
VLSI Design
Kapil Bajaj
Broadcom
VLSI Design
Eligibility
Guidelines
Guidelines
- Teams of 4 members; students from different academic batches are welcome
- Open to bachelor’s students only
- All team members must be IEEE CAS members — or apply for membership while registering
- Regular syncs with mentors throughout the internship
- A roadmap to the global IEEE CASS Student Design Competition
- The registration fee is reimbursed on successful completion
Who is eligible
- Students currently in, or moving into, their 5th or 7th semester within a month
- Not eligible: students graduating within a month, or already graduated
- Not eligible: students in their 1st or 3rd semester
Registration · closed
Registration fee
Limited slots were available.
IEEE CAS member
₹250/ person
Reimbursed on completion
IEEE member
₹500/ person
Non-IEEE
₹800/ person
01
Last date to apply was 8 August 2024; the internship started on 12 August 2024.
02
Program contacts: Sriniketh S S and Dr. Kiran A Gupta.
Registration closed
Good to know
Frequently asked questions
What is the mode of the internship?
Online, except for the final presentation (in November).
What is the duration of the internship?
12 weeks.
Is the payment per person or per group?
Registration is by group; the fee is calculated per person.
How many students per team?
4.
The series
Every edition of SIP
Interested in the next SIP?
Write to the IEEE CAS Bangalore Chapter to hear when the next edition opens.