Event concluded  ·  Held 18 November 2023 at Hilton Bangalore Embassy GolfLinks  ·  Hybrid
IEEE CAS Bangalore Chapter · CAS Industry Forum 2.0

Chip VerificationThe New Frontiers

An industry forum on the latest advances in chip verification.

CASIF23 2.0 · With the IEEE Bangalore Section · Sponsored by Synopsys

Date18 Nov 2023
Time9:00 AM – 5:00 PM
VenueHilton, Embassy GolfLinks
ModeHybrid
CASIF 2.0 poster — Chip Verification: The New Frontiers, 18 November 2023
Official poster
About the forum

Why verification, why now

In today’s intricate chip-design landscape, verification and validation have taken centre stage: verification engineers outnumber designers by about 5 to 1 on most processor projects, and verification takes around 70% of the budget.

CASIF 2.0 brought together experts from EDA companies, semiconductor makers, HPC specialists and academia to explore the latest in chip verification — through a keynote, a tutorial, technical talks and networking, in person and online.

1
Keynote
1
Tutorial
4
Technical talks
10
Guests & speakers
Speakers & guests

Who spoke

Achutha Kiran Kumar V M
Chief Guest · Speaker
Achutha Kiran Kumar V M
Intel Fellow & GM, Formal Verification CTO, Intel
Dr. Prasant Misra
Chief Guest
Dr. Prasant Misra
Vice-Chair, Industry Engagement, IEEE Bangalore Section
Dr. Chengappa M R
Chief Guest
Dr. Chengappa M R
Secretary, IEEE Bangalore Section
Subind Kumar
Chief Guest
Subind Kumar
Corporate VP & India Site Head, Western Digital
Dr. Raj S Mitra
Chief Guest
Dr. Raj S Mitra
Director, Cisma Consultants
Dr. Pallab Dasgupta
Keynote
Dr. Pallab Dasgupta
Research & Innovation, Formal Verification, Synopsys
Dr. Vivek Tovinakere
Tutorial
Dr. Vivek Tovinakere
Platform Power Architect (FPGAs), Intel
Pradeep Babu
Speaker
Pradeep Babu
Director, Engineering, Qualcomm
Nilesh Dhavlikar
Speaker
Nilesh Dhavlikar
Senior Director, Engineering, Qualcomm
Dr. Srinivas Pinisetty
Speaker
Dr. Srinivas Pinisetty
Faculty, School of Electrical Sciences, IIT Bhubaneswar
Agenda

18 November · schedule

8:30 – 9:00 AM
Registration
9:00 – 10:00 AM
Inauguration and opening ceremony
10:15 – 11:05 AM
Keynote — Verification: latest trends, challenges and roadmapDr. Pallab Dasgupta, Synopsys
11:05 – 11:20 AM
Tea break
11:20 AM – 12:20 PM
Tutorial — SoC-level verification: PnPDr. Vivek Tovinakere, Intel
12:20 – 1:00 PM
Technical Talk 1 — Low-power verification: state of the art, challenges and roadmapPradeep Babu, Qualcomm
1:00 – 1:50 PM
Lunch
1:50 – 2:30 PM
Technical Talk 2 — Formal is the new normalAchutha Kiran Kumar V M, Intel
2:30 – 3:10 PM
Technical Talk 3 — Post-silicon verificationNilesh Dhavlikar, Qualcomm
3:10 – 3:30 PM
Tea break
3:30 – 4:10 PM
Technical Talk 4 — Safety and security verification: challenges and roadmapDr. Srinivas Pinisetty, IIT Bhubaneswar
4:10 – 4:35 PM
Sponsor talks
4:35 – 5:00 PM
Closing ceremony
Profiles

Guests and speakers

Dr. Pallab Dasgupta

Leads Research and Innovation on Formal Verification at Synopsys, Sunnyvale, with more than 25 years in formal verification. He was a professor and Dean of Sponsored Research at IIT Kharagpur, where his research group on formal methods and EDA produced over 250 publications.

Achutha Kiran Kumar V M

A home-grown Intel Fellow who joined Intel from IISc Bangalore. He leads the Formal Verification Central Tech Office, is co-author of Formal Verification — An Essential Toolkit for Modern VLSI Design, and has 100+ publications and 15 best-paper awards.

Nilesh Dhavlikar

20+ years in VLSI, specialising in SoC pre- and post-silicon validation. He leads Qualcomm’s SoC Validation & Emulation team for Snapdragon mobile SoCs across handset, compute, automotive, IoT and XR.

Dr. Srinivas Pinisetty

Assistant Professor in the School of Electrical Sciences at IIT Bhubaneswar, with a PhD from INRIA / University of Rennes 1. His research covers formal methods, and runtime verification and enforcement in particular.

Dr. Vivek Tovinakere

FPGA Platform Power Architect in Intel’s Programmable Solutions Group, with about 22 years in the semiconductor industry on power and performance modelling for client SoCs, HPC and FPGAs. PhD from the University of Rennes 1; IEEE Senior Member.

Pradeep Babu

24 years in SoC design verification and validation; an expert in automotive functional-safety verification who led multiple ASIL-D/B SoCs at Qualcomm and holds 2 US patents.

Dr. Prasant Misra

Chair of the IEEE Computer Society Bangalore Chapter and Vice-Chair (Industry Engagements) of the IEEE Bangalore Section; he has served on the editorial boards of IEEE Communications Magazine and IEEE ITS Magazine.

Dr. Chengappa M R

Lead Engineer and Expert Technologist at Hewlett Packard Enterprise, leading customer consulting on end-to-end vRAN architecture and contributing to O-RAN Alliance working groups.

Subind Kumar

Leads Western Digital’s global product-development team for the Content Solutions Group — SD/microSD, USB, CFast and retail SSD products.

Dr. Raj S Mitra

A veteran of EDA and verification (Cadence, Synopsys, Interra, and Head of EDA at Texas Instruments Bangalore), now Director at Cisma Consultants, working on formal verification, portable stimulus and machine learning.

Getting there

Venue

Venue

Hilton Bangalore Embassy GolfLinks

Embassy GolfLinks Business Park, Intermediate Ring Road, Bengaluru

Sponsors & partners

With support from

Sponsor
Organised with
The series

Every CAS Industry Forum

The team

Organizing committee

Affiliations as they were in November 2023.

Ayan Datta
Ayan Datta
Technologist, Western Digital
Apurva Kumar
Apurva Kumar
Director of Engineering, Quest Global
Sudipto Das
Sudipto Das
AVP, Quest Global
Abhijeet Khopkar
Abhijeet Khopkar
Director R&D, Synopsys
Dr. Sumantra Sarkar
Dr. Sumantra Sarkar
MTS, AMD
Surinder Sood
Surinder Sood
Principal Engineer, Arm Embedded Technologies
Kiran K R
Kiran K R
Digital Design Engineer, Intel
Dr. Srobona Mitra
Dr. Srobona Mitra
Senior Staff Engineer / Manager, Qualcomm

Questions about CASIF?

Write to the organising team at the IEEE CAS Bangalore Chapter — we’re happy to help.