Chip VerificationThe New Frontiers
An industry forum on the latest advances in chip verification.
CASIF23 2.0 · With the IEEE Bangalore Section · Sponsored by Synopsys

Why verification, why now
In today’s intricate chip-design landscape, verification and validation have taken centre stage: verification engineers outnumber designers by about 5 to 1 on most processor projects, and verification takes around 70% of the budget.
CASIF 2.0 brought together experts from EDA companies, semiconductor makers, HPC specialists and academia to explore the latest in chip verification — through a keynote, a tutorial, technical talks and networking, in person and online.
Who spoke










18 November · schedule
Guests and speakers
Dr. Pallab Dasgupta
Leads Research and Innovation on Formal Verification at Synopsys, Sunnyvale, with more than 25 years in formal verification. He was a professor and Dean of Sponsored Research at IIT Kharagpur, where his research group on formal methods and EDA produced over 250 publications.
Achutha Kiran Kumar V M
A home-grown Intel Fellow who joined Intel from IISc Bangalore. He leads the Formal Verification Central Tech Office, is co-author of Formal Verification — An Essential Toolkit for Modern VLSI Design, and has 100+ publications and 15 best-paper awards.
Nilesh Dhavlikar
20+ years in VLSI, specialising in SoC pre- and post-silicon validation. He leads Qualcomm’s SoC Validation & Emulation team for Snapdragon mobile SoCs across handset, compute, automotive, IoT and XR.
Dr. Srinivas Pinisetty
Assistant Professor in the School of Electrical Sciences at IIT Bhubaneswar, with a PhD from INRIA / University of Rennes 1. His research covers formal methods, and runtime verification and enforcement in particular.
Dr. Vivek Tovinakere
FPGA Platform Power Architect in Intel’s Programmable Solutions Group, with about 22 years in the semiconductor industry on power and performance modelling for client SoCs, HPC and FPGAs. PhD from the University of Rennes 1; IEEE Senior Member.
Pradeep Babu
24 years in SoC design verification and validation; an expert in automotive functional-safety verification who led multiple ASIL-D/B SoCs at Qualcomm and holds 2 US patents.
Dr. Prasant Misra
Chair of the IEEE Computer Society Bangalore Chapter and Vice-Chair (Industry Engagements) of the IEEE Bangalore Section; he has served on the editorial boards of IEEE Communications Magazine and IEEE ITS Magazine.
Dr. Chengappa M R
Lead Engineer and Expert Technologist at Hewlett Packard Enterprise, leading customer consulting on end-to-end vRAN architecture and contributing to O-RAN Alliance working groups.
Subind Kumar
Leads Western Digital’s global product-development team for the Content Solutions Group — SD/microSD, USB, CFast and retail SSD products.
Dr. Raj S Mitra
A veteran of EDA and verification (Cadence, Synopsys, Interra, and Head of EDA at Texas Instruments Bangalore), now Director at Cisma Consultants, working on formal verification, portable stimulus and machine learning.
Venue
Hilton Bangalore Embassy GolfLinks
Embassy GolfLinks Business Park, Intermediate Ring Road, Bengaluru
With support from




Every CAS Industry Forum
Organizing committee
Affiliations as they were in November 2023.








Questions about CASIF?
Write to the organising team at the IEEE CAS Bangalore Chapter — we’re happy to help.