RTL Front-EndWorkshop
RTL design using Verilog, with ModelSim-based simulation.
With the IEEE Bangalore Section, the IEEE CAS Chapter, VVCE and the IEEE VVCE Student Branch
Why front-end design?
Almost every hardware multinational has RTL design teams — most of them in Bengaluru and across India — and those teams keep growing.
RTL entry is a critical step in the design cycle: it turns the micro-architectural specification into implementable constructs, which then feed the physical-design flow. This six-day hybrid workshop covered RTL design in Verilog with ModelSim-based simulation.
Hybrid, over six days
Day 1 · In person
2 September 2023 · 9:30 AM onwards · VVCE, Mysuru
Introductory material and familiarity with the tool setup. Five problem statements were introduced so students could attempt them before the online sessions.
Days 2 – 6 · Online
4 – 8 September 2023 · 5:00 – 6:30 PM
One problem statement a day: the speaker walked through their implementation and took questions from the students.
Who taught it
Registration fee
IEEE CAS member
IEEE member
Non-IEEE
Venue
Organised with
Organizing committee
Affiliations as they were in August 2023.
Questions?
Write to the IEEE CAS Bangalore Chapter — we’re happy to help.