RTL FRONT END WORKSHOP
Focus: RTL Design using Verilog + Modelsim based Simulation
Why Front End design?
Almost all Hardware MNCs have RTL design teams and the trend is towards expansion of those teams, majority of them based at Bangalore & India. RTL entry is a critical aspect of the design cycle that implements the micro-architectural specs into implementable constructs, which then serve as an input to the Physical Design Flow.
Last chance to avail discounts until August 29th, 9pm – Act swiftly!
SPEAKERS
Hariprasad Bhat
Manager – RTL Design & FPGA Implementation at Lekha Wireless Solutions Pvt. Ltd.
Jayesh Tanwani
Engineering Manager at Intel Corporation and Vice Chair IEEE CAS Member Activity
Nithin Pinto
Senior FPGA Engineer at Lekha Wireless Solutions Pvt. Ltd.
Karthik S Bhat
Tech Lead at Lekha Wireless Solutions Pvt. Ltd.
SCHEDULE
COMPLETE SCHEDULE
DAY 1
REGISTRATION
Audience: BE/BTech 4th Sem & above, M.Tech any Sem.
Format – Hybrid
Day 1: In person (Introductory Material + Setup familiarity)
Day 2 – 6: Sessions Online. We will work out 5 problem statements. This problem details will be discussed in the Day 1 sessions so that it can be tried out by the students before the session. Presenter/speaker will explain his implementation and open for any queries from the students. (5PM – 6.30PM)
ORGANIZING COMMITTEE
Ayan Datta
Technologist Western Digital
Hariprasad Bhat
Manager LWS
Dr. Geethashree A
Associate Professor VVCE, Mysuru
Kiran K R
Digital Design Engineer Intel
Prajwal A Gujjar
Chair, CAS Chapter, IEEE VVCE
Execom, IEEE VVCE SB
Execom, IEEE VVCE SB
Mayur V
Mayur V, Chair, IEEE VVCE SB
SAC-Lead, IEEE Mysore Subsection
SAC-Lead, IEEE Mysore Subsection